Method for suppressing errors, and associated memory device and controller thereof

ABSTRACT

A method for suppressing errors is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: according to an address of data to be written into or read from the Flash memory, determining whether to utilize an original seed as an input seed of a randomizer/derandomizer, where the randomizer/derandomizer is arranged to generate a random function according to the input seed, with the random function being utilized for adjusting a plurality of bits of the data bit by bit, and with regard to at least each block of the blocks, a value of the original seed remains unvaried; and when it is determined that the original seed should not be utilized as the input seed, generating the random function according to a new seed to adjust the data.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to access to a Flash memory, and moreparticularly, to a method for suppressing errors, and to an associatedmemory device and a controller thereof.

2. Description of the Prior Art

As technologies of Flash memories progress in recent years, many kindsof portable memory devices (e.g. memory cards respectively complyingwith SD/MMC, CF, MS, and XD standards) or solid state drives (SSDs)equipped with Flash memories are widely implemented in variousapplications. Therefore, the control of access to Flash memories inthese memory devices has become an important issue.

Taking NAND Flash memories as an example, they can mainly be dividedinto two types, i.e. Single Level Cell (SLC) Flash memories and MultipleLevel Cell (MLC) Flash memories. Each transistor that is considered amemory cell in SLC Flash memories only has two charge levels thatrespectively represent a logical value 0 and a logical value 1. Inaddition, the storage capability of each transistor that is considered amemory cell in MLC Flash memories can be fully utilized. Morespecifically, the voltage for driving memory cells in the MLC Flashmemories is typically higher than that in the SLC Flash memories, anddifferent voltage levels can be applied to the memory cells in the MLCFlash memories in order to record information of at least two bits (e.g.binary values 00, 01, 11, or 10) in a transistor that is considered amemory cell. Theoretically, the storage density of the MLC Flashmemories may reach twice the storage density of the SLC Flash memories,which is considered good news for NAND Flash memory manufacturers whoencountered a bottleneck of NAND Flash technologies.

As MLC Flash memories are cheaper than SLC Flash memories, and arecapable of providing higher capacity than SLC Flash memories while thespace is limited, MLC Flash memories have been a main stream forimplementation of most portable memory devices on the market. However,various problems of the MLC Flash memories have arisen due to theirunstable characteristics. In order to ensure that the access control ofa memory device over the Flash memory therein can comply with relatedstandards, the controller of the Flash memory should have some handlingmechanisms in order to properly handle its data access operations.

According to the related art, the memory device having theaforementioned handling mechanisms may still suffer from somedeficiencies. For example, due to usage behaviors of the user, data ofsome specific data patterns would probably be constantly written intothe Flash memory, where these specific data patterns may easily causeerrors such as write/program errors, read errors, etc. Although thememory device may be equipped with a randomizer for adjusting data inorder to solve such a problem, the data after adjustment is typicallynot random enough due to the conventional low cost design. According tothe typical implementation of the related art, with regard to eachsector, the value of an input seed of the randomizer remains unvaried(i.e. for each sector, the input seed always has the same value), so theproblem mentioned above are not really resolved. Therefore, a novelmethod is required for performing data pattern management regarding dataaccessed by the controller in order to reduce the probability of erroroccurrence.

SUMMARY OF THE INVENTION

It is therefore an objective of the claimed invention to provide amethod for suppressing errors, and to provide an associated memorydevice and a controller thereof, in order to solve the above-mentionedproblems.

According to a preferred embodiment of the claimed invention, a methodfor suppressing errors is provided. The method is applied to acontroller of a Flash memory, where the Flash memory comprises aplurality of blocks. The method comprises: according to an address ofdata to be written into or read from the Flash memory, determiningwhether to utilize an original seed as an input seed of arandomizer/derandomizer, wherein the randomizer/derandomizer is arrangedto generate a random function according to the input seed, with therandom function being utilized for adjusting a plurality of bits of thedata bit by bit, and with regard to at least each block of the blocks, avalue of the original seed remains unvaried; when it is determined thatthe original seed should be utilized as the input seed, inputting theoriginal seed into the randomizer/derandomizer, in order to generate therandom function according to the original seed to adjust the data; andwhen it is determined that the original seed should not be utilized asthe input seed, inputting a new seed into the randomizer/derandomizer,in order to generate the random function according to the new seed toadjust the data.

While the method mentioned above is disclosed, an associated memorydevice is further provided. The memory device comprises: a Flash memorycomprising a plurality of blocks; and a controller arranged to accessthe Flash memory and manage the plurality of blocks, and furthersuppress errors regarding data accessed by the controller itself. Inaddition, the controller comprises a randomizer/derandomizer arranged togenerate a random function according to an input seed, with the randomfunction being utilized for adjusting a plurality of bits of the databit by bit when the controller receives a write/read command, whereinthe write/read command is utilized for instructing the controller towrite the data into/read the data from the Flash memory, the controllerdetermines whether to utilize an original seed as the input seedaccording to an address of the data, and with regard to at least eachblock of the blocks, a value of the original seed remains unvaried.Additionally, when it is determined that the original seed should beutilized as the input seed, the controller inputs the original seed intothe randomizer/derandomizer, in order to generate the random functionaccording to the original seed to adjust the data; and when it isdetermined that the original seed should not be utilized as the inputseed, the controller inputs a new seed into the randomizer/derandomizer,in order to generate the random function according to the new seed toadjust the data.

While the method mentioned above is disclosed, a controller of a memorydevice is further provided, wherein the controller is utilized foraccessing a Flash memory comprising a plurality of blocks. Thecontroller comprises: a read only memory (ROM) arranged to store aprogram code; a microprocessor arranged to execute the program code tocontrol access to the Flash memory and manage the plurality of blocks,and further suppress errors regarding data accessed by the controlleritself; and a randomizer/derandomizer arranged to generate a randomfunction according to an input seed, with the random function beingutilized for adjusting a plurality of bits of the data bit by bit whenthe controller receives a write/read command, wherein the write/readcommand is utilized for instructing the controller to write the datainto/read the data from the Flash memory, the controller determineswhether to utilize an original seed as the input seed according to anaddress of the data, and with regard to at least each block of theblocks, a value of the original seed remains unvaried. In addition, whenit is determined that the original seed should be utilized as the inputseed, the controller inputs the original seed into therandomizer/derandomizer, in order to generate the random functionaccording to the original seed to adjust the data; and when it isdetermined that the original seed should not be utilized as the inputseed, the controller inputs a new seed into the randomizer/derandomizer,in order to generate the random function according to the new seed toadjust the data.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a memory device according to a first embodimentof the present invention.

FIG. 2 is a flowchart of a method for suppressing errors according toone embodiment of the present invention.

FIGS. 3A-3B respectively illustrate a conversion matrix and acorresponding conversion circuit involved with the method shown in FIG.2 according to an embodiment of the present invention.

FIG. 4A illustrates some implementation details of the seed generatorshown in FIG. 1 that are involved with the method shown in FIG. 2according to an embodiment of the present invention.

FIG. 4B illustrates some implementation details of the seed generatorshown in FIG. 1 that are involved with the method shown in FIG. 2according to another embodiment of the present invention.

FIG. 5 illustrates a series of values involved with the embodiment shownin FIG. 4B, while the series of values can be generated in a situationwhere the number of cycles of operations of the randomizer/derandomizershown in FIG. 1 is not limited.

FIG. 6 is a diagram of a seed generator of a memory device according toa second embodiment of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 1, which illustrates a diagram of a memory device100 according to a first embodiment of the present invention. Inparticular, the memory device 100 of this embodiment is a portablememory device, examples of which may include, but not limited to, memorycards complying with SD/MMC, CF, MS, or XD standards, and UniversalSerial Bus (USB) Flash drives (which can be referred to as USB Flashdisks). The memory device 100 comprises a Flash memory 120, and furthercomprises a controller arranged to access the Flash memory 120, wherethe aforementioned controller of this embodiment is a memory controller110. According to this embodiment, the memory controller 110 comprises amicroprocessor 112, a read only memory (ROM) 112M, a control logic 114,a buffer memory 116, and an interface logic 118. In addition, thecontrol logic 114 comprises an adjustment unit 114A, a seed generator114G, a multiplexer 114M (labeled “MUX” in FIG. 1), and arandomizer/derandomizer 114R. In practice, the adjustment unit 114A canbe an exclusive OR (XOR) gate or an adder. Please note that the portablememory device is taken as an example of the memory device 100 in thisembodiment. This is for illustrative purposes only, and is not meant tobe a limitation of the present invention. According to a variation ofthis embodiment, the memory device 100 can be a solid state drive (SSD).

In this embodiment, the ROM 112M is arranged to store a program code112C, and the microprocessor 112 is arranged to execute the program code112C to control the access to the Flash memory 120. Typically, the Flashmemory 120 comprises a plurality of blocks, and the controller (e.g. thememory controller 110 that executes the program code 112C by utilizingthe microprocessor 112) performs data erasure operations on the Flashmemory 120 by erasing in units of blocks. In addition, a block can beutilized for recording a specific amount of pages, where the controllermentioned above performs data writing operations on the Flash memory 120by writing/programming in units of pages.

In practice, the memory controller 110 that executes the program code112C by utilizing the microprocessor 112 is capable of performingvarious control operations by utilizing the internal components withinthe memory controller 110. For example, the memory controller 110utilizes the control logic 114 to control access to the Flash memory 120(e.g. operations of accessing at least one block or at least one page),utilizes the buffer memory 116 to perform buffering operations for thememory controller 110, and utilizes the interface logic 118 tocommunicate with a host device. According to this embodiment, inaddition to accessing the Flash memory 120, the memory controller 110 iscapable of properly managing the plurality of blocks.

In addition, the memory controller 110 can further suppress errorsregarding data accessed by the memory controller 110 itself (e.g. thedata D_(B) shown in FIG. 1), and more particularly, suppress errors byutilizing operations of the randomizer/derandomizer 114R. Morespecifically, the randomizer/derandomizer 114R is arranged to generate arandom function according to an input seed 114S, with the randomfunction being utilized for adjusting a plurality of bits of the data(e.g. the data D_(B)) bit by bit when the controller receives awrite/read command, where the write/read command is utilized forinstructing the controller to write the data into/read the data from theFlash memory 120. As a result, the adjustment unit 114A shown in FIG. 1adjusts the data D_(B) according to the random sequence 114RS (i.e. thesequence of the random function mentioned above) to generate theadjusted data D_(A). For example, in a situation where the write/readcommand mentioned above represents a write command, when the data pathpassing through the adjustment unit 114A represents a write path, thedata D_(B) may represent the data to be written into the Flash memory120 by the controller, and the data D_(A) may represent the adjusteddata for being written. In anther example, in a situation where thewrite/read command mentioned above represents a read command, when thedata path passing through the adjustment unit 114A represents a readpath, the data D_(B) may represent the data read from the Flash memory120 by the controller, and the data D_(A) may represent the adjusteddata for being further processed to be sent back to the host device. Inpractice, the memory controller 110 that executes the program code 112Cby utilizing the microprocessor 112 can generate control signals C0, C1,and C2, in order to control the seed generator 114G, the multiplexer114M, and the randomizer/derandomizer 114R.

In this embodiment, the control signal C0 may carry at least one indexfor indicating the sector, the word, and/or the byte that the data D_(B)corresponds to, and more particularly, for indicating the portioncurrently being processed within the data D_(B). In addition to thecontrol signal C0, the seed generator 114G of this embodiment furtherreceives the original seed 114B. As a result, according to the controlof the control signal C0, the seed generator 114G can adjust theoriginal seed 114B correspondingly to generate the new seed 114N, wherethe new seed 114N corresponds to the index, and the new seed 114N istypically different from the original seed 114B since the seed generator114G (whose implementation details will be described later) is properlydesigned. Thus, even in a situation where the original seed 114B isgenerated by utilizing the architecture of the conventional low costdesign, causing repeated occurrence of the same value of the originalseed 114B, there is no repeated occurrence of the same value of the newseed 114N. In addition, the control of the control signal C1 is utilizedfor controlling multiplexing operations of the multiplexer 114M, inorder to make the multiplexer 114M correspondingly multiplex theoriginal seed 114B or the new seed 114N as the input seed 114S of therandomizer/derandomizer 114R. Additionally, the control of the controlsignal C2 is utilized for controlling loading operations of therandomizer/derandomizer 114R, in order to make therandomizer/derandomizer 114R be able to correctly load the input seed114S.

Based upon the architecture shown in FIG. 1, as there is no repeatedoccurrence of the same value of the new seed 114N, as long as theoperations of selecting the original seed 114B or the new seed 114N asthe input seed 114S can be properly controlled, the related art problemthat the adjusted data is not random enough is no longer an issue. As aresult, the original seed 114B can still be generated by utilizing thearchitecture of the conventional low cost design. In this embodiment,with regard to at least each block of the blocks, the value of theoriginal seed 114B remains unvaried, where for each block of the blocks,the same original seed 114B is utilized. For example, with regard toeach page of each block, the value of the original seed 114B remainsunvaried. More particularly, with regard to each sector of each block,the value of the original seed 114B remains unvaried. Please refer toFIG. 2 for related details of error suppression performed by the memorycontroller 110.

FIG. 2 is a flowchart of a method 910 for suppressing errors accordingto one embodiment of the present invention. The method can be applied tothe memory device 100 shown in FIG. 1, and more particularly, to thecontroller mentioned above (e.g. the memory controller 110 that executesthe program code 112C by utilizing the microprocessor 112). In addition,the method can be implemented by utilizing the memory device 100 shownin FIG. 1, and more particularly, by utilizing the controller mentionedabove. The method 910 is described as follows.

In Step 912, the controller determines whether to utilize the originalseed 114B as the input seed 114S of the randomizer/derandomizer 114Raccording to an address of the data to be written into or read from theFlash memory 120 (e.g. the data D_(B)). When it is determined that theoriginal seed 114B should be utilized as the input seed 114S, Step 914-1is entered; otherwise (i.e. when it is determined that the original seed114B should not be utilized as the input seed 114S), Step 914-2 isentered.

In Step 914-1, the controller inputs the original seed 114B into therandomizer/derandomizer 114R, in order to generate the random functionaccording to the original seed 114B to adjust the data.

In Step 914-2, the controller inputs the new seed 114N into therandomizer/derandomizer 114R, in order to generate the random functionaccording to the new seed 114N to adjust the data.

In this embodiment, when the address mentioned in Step 912 falls withina predetermined range, the controller determines that the original seed114B should be utilized as the input seed 114S. In addition, when theaddress does not fall within the predetermined range, the controllerdetermines that the original seed 114B should not be utilized as theinput seed 114S. For example, with regard to each block, the value ofthe original seed 114B remains unvaried, and in this situation, thepredetermined range may correspond to a block, a page, a sector, or astorage unit that is smaller than the sector. In another example, withregard to each page of each block, the value of the original seed 114Bremains unvaried, and in this situation, the predetermined range maycorrespond to a page, a sector, or a storage unit that is smaller thanthe sector, where the page mentioned in this situation may comprisemultiple sectors. In another example, with regard to each sector of eachblock, the value of the original seed 114B remains unvaried, and in thissituation, the predetermined range may correspond to a sector or astorage unit that is smaller than the sector.

According to this embodiment, the seed generator 114G is arranged toadjust the original seed 114B to generate the new seed 114N, where theoriginal seed 114B comprises a plurality of bits, and the new seed 114Ncomprises a plurality of bits. In addition, the seed generator 114Gstores one or more predetermined matrixes, and more particularly, aplurality of predetermined matrixes A^(Z(1)), A^(Z(2)), . . . , andA^(Z(X)), where the notation A represents a conversion matrix of therandomizer/derandomizer 114R regarding the random sequence 114RS, and inthis embodiment, the seed generator 114G can be regarded as a circuitfor implementing the aforementioned one or more predetermined matrixes.As a result, the seed generator 114G utilizes the original seed 114B anda specific predetermined matrix of the one or more predeterminedmatrixes to perform operations, in order to generate the new seed 114N.For example, in a situation where the original seed 114B and the newseed 114N respectively comprise W bits, the conversion matrix A is a Wby W matrix, and the predetermined matrixes A^(Z(1)), A^(Z(2)), . . . ,and A^(Z(X)) mentioned above are also W by W matrixes, respectively.Please note that the conversion matrix A is not limited to be a squarematrix. In another example, the conversion matrix A can be a W by Mmatrix or an M by W matrix as long as the conversion matrix A can beutilized for performing multiplication operations on the original seed114B, where M is not equal to W.

Here, the random sequence 114RS can be expressed as the sequence{RS(t)|t is an integer} (with t being an index corresponding to time),and the relationship between any value RS(t) of this sequence and thenext value RS(t+1) thereof can be expressed according to the followingequation:RS(t+1)=A*RS(t);

Thus, when the value of the input seed 114S is equal to RS(t₀), byutilizing the conversion expressed by the above equation, therandomizer/derandomizer 114R can generate at least one portion (e.g. aportion or all) of the sequence {RS(t)}, and more particularly, theportion starting from RS(t₀+1), i.e. the sequence {RS(t)|t≧(t₀+1)}.

FIGS. 3A-3B respectively illustrate the conversion matrix A and thecorresponding conversion circuit 300 involved with the method 910 shownin FIG. 2 according to an embodiment of the present invention, where theconversion circuit 300 is positioned within the randomizer/derandomizer114R, and the conversion circuit 300 comprises W registers 310-0, 310-1,. . . , and 310-(W−1) and an XOR gate 320 (labeled “XOR” in FIG. 3B). Ina situation where W=5, the registers 310-0, 310-1, 310-2, 310-3, and310-4 (respectively labeled “RS(t; 0)”, “RS(t; 1)”, “RS(t; 2)”, “RS(t;3)”, and “RS(t; 4)” in FIG. 3B) store respective bits RS(t; 0), RS(t;1), RS(t; 2), RS(t; 3), and RS(t; 4) of the binary form of the valueRS(t), respectively. According to the architecture shown in FIG. 3B, therandomizer/derandomizer 114R can generate at least one portion of thesequence {RS(t)}, such as a portion or all of the sequence {RS(t)}.

FIG. 4A illustrates some implementation details of the seed generatorshown in FIG. 1 that are involved with the method 910 shown in FIG. 2according to an embodiment of the present invention. According to thisembodiment, the seed generator 114G comprises an adjustment circuit 410and a storage unit. The storage unit 420 stores X predetermined matrixesA^(Z(1)), A^(Z(2)), . . . , and A^(Z(X)), where Z(1), Z(2), . . . , andZ(X) are all positive integers, and more particularly, positive integersthat are different from each other. In addition, according to theaforementioned at least one index, the seed generator 114G (and moreparticularly, the adjustment circuit 410) selects a correspondingpredetermined matrix A^(Z(x)) from the X predetermined matrixesA^(Z(1)), A^(Z(2)), . . . , and A^(Z(X)), where x=1, 2, . . . , or X,and the control signal C0 carries the aforementioned at least one index.As a result, the seed generator 114G utilizes the predetermined matrixA^(Z(x)) to adjust the original seed 114B, in order to generate the newseed 114N. According to a special case of this embodiment, Z(1), Z(2), .. . , and Z(X) can be an arithmetic sequence. According to anotherspecial case of this embodiment, Z(1), Z(2), . . . , and Z(X) can be anarithmetic sequence, and the common difference of successive members ofthis arithmetic sequence Z(1), Z(2), . . . , and Z(X) is equal to Z(1).

FIG. 4B illustrates some implementation details of the seed generator114G shown in FIG. 1 that are involved with the method 910 shown in FIG.2 according to another embodiment of the present invention, where thisembodiment is a special case of the embodiment shown in FIG. 4A. In thisembodiment, Z(x)=(1024*x) and X=3, and each page comprises 4 kilobytesand each sector comprises 1 kilobyte (i.e. each page comprises 4sectors), given that 1 kilobyte is 1024 bytes. As shown in FIG. 4B, thestorage unit 420 stores 3 predetermined matrixes A¹⁰²⁴, A²⁰⁴⁸, andA³⁰⁷². Please refer to FIG. 5 for better comprehension. FIG. 5illustrates a series of values involved with the embodiment shown inFIG. 4B, while the series of values can be generated in a situationwhere the number of cycles of operations of the randomizer/derandomizer114R shown in FIG. 1 is not limited. As shown in FIG. 5, the series ofvalues comprise {RS(1), RS(2), RS(3), . . . , RS(1024)}, {RS(1025), . .. , RS(2048)}, {RS(2049), . . . , RS(3072)}, {RS(3073), . . . ,RS(4096)}, and {RS(4097), . . . , RS(32K)}, where RS(32K) representsRS(32768). In a situation where W=8, each value of the series of valuesfalls within the range of the interval [0, 255]. Here, the numbers inthe respective circles shown in FIG. 5 are taken as examples of theseries of values. This is for illustrative purposes only, and is notmeant to be a limitation of the present invention. According to avariation of this embodiment, these numbers in the respective circlesshown in FIG. 5 can be varied.

According to this embodiment, after the value RS(32K) is generated, thenext value to be generated (i.e. the value to be subsequently generatedafter generating the value RS(32K)) is the first value RS(1) of thisseries of values, where this series of values can be generatedrepeatedly. In general, this series of values can be divided into (Y+1)portions as follows:

-   {RS(Z(0)+1), RS(Z(0)+2), . . . , RS(Z(1))};-   {RS(Z(1)+1), RS(Z(1)+2), . . . , RS(Z(2))};-   {RS(Z(2)+1), RS(Z(2)+2), . . . , RS(Z(3))};    . . . and-   {RS(Z(Y)+1), RS(Z(Y)+2), . . . , RS(Z(Y+1))};    where Y=31 in this embodiment.

Suppose that after the controller inputs the original seed 114B into therandomizer/derandomizer 114R and a cycle goes by, the first value thatappears within the random sequence 114RS is RS(1), and the predeterminedrange utilized by the controller corresponds to a sector (whichcomprises 1 kilobyte), and more particularly, the first sector of anypage. As a result, when the address mentioned in Step 912 falls withinthe predetermined range, which means the address represents the firstsector of a certain page, the controller determines that the originalseed 114B should be utilized as the input seed 114S. In addition, whenthe address does not fall within the predetermined range, and moreparticularly, when the address represents the (v+1)^(th) sector of acertain page, under control of the controller, the seed generator 114Gcan utilize the original seed 114B and the predetermined matrix A^(Z(v))to perform operations, in order to generate the new seed 114N, wherev=1, 2, or 3. Similar descriptions for this embodiment are not repeatedin detail here.

According to a variation of this embodiment, the predetermined rangeutilized by the controller corresponds to a sector (which comprises 1kilobyte), and more particularly, the first sector of each set ofsectors. In this embodiment, each set of sectors may comprise 32sectors. In addition, the storage unit 420 stores 31 predeterminedmatrixes A¹⁰²⁴, A²⁰⁴⁸, A³⁰⁷², . . . and A^(31K), where A^(31K)represents A³¹⁷⁴⁴. As a result, when the address mentioned in Step 912falls within the predetermined range, which means the address representsthe first sector of a certain set of sectors, the controller determinesthat the original seed 114B should be utilized as the input seed 114S.Additionally, when the address does not fall within the predeterminedrange, and more particularly, when the address represents the (v+1)^(th)sector of a certain set of sectors, under control of the controller, theseed generator 114G can utilize the original seed 114B and thepredetermined matrix A^(Z(v)) to perform operations, in order togenerate the new seed 114N, where v=1, 2, . . . , or 31. Similardescriptions for this variation are not repeated in detail here.

FIG. 6 is a diagram of a seed generator 114G′ of a memory device 200according to a second embodiment of the present invention, where thisembodiment is a variation of the first embodiment. The multiplexer 114Mof this embodiment is integrated into the seed generator 114G mentionedabove, and in response to the change of the architecture, the seedgenerator of this embodiment is labeled using a similar notation such as114G′, where the seed generator 114G′ inputs the aforementioned inputseed 114S into the randomizer/derandomizer 114R mentioned above. Thus,the memory device 200 of this embodiment (or the memory controller 210thereof) can be distinguished from the memory device 100 shown in FIG. 1(or the memory controller 110 thereof) according to whether themultiplexer 114M is positioned within the seed generator. Similardescriptions for this embodiment are not repeated in detail here.

It is an advantage of the present invention that, by properly designingthe seed generator 114G accompanied with associated control (e.g. thecontrol signals C0, C1, and C2), the present invention can properlyperform data pattern management regarding data accessed by thecontroller, in order to reduce the probability of error occurrence. Inaddition, implementing according to any of the respectiveembodiments/variations disclosed above will not cause unreasonableadditional costs, while the original seed 114B can still be generated byutilizing the architecture of the conventional low cost design.Therefore, by implementing based upon one or more of theembodiments/variations disclosed above, the related art problems can beresolved without greatly increasing the overall costs.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention.

What is claimed is:
 1. A method for suppressing errors, the method beingapplied to a controller of a Flash memory, the Flash memory comprising aplurality of blocks, the method comprising: according to an address ofdata to be written into or read from the Flash memory, determiningwhether to utilize an original seed as an input seed of arandomizer/derandomizer, wherein the randomizer/derandomizer is arrangedto generate a random function according to the input seed, with therandom function being utilized for adjusting a plurality of bits of thedata bit by bit, and with regard to at least each block of the blocks, avalue of the original seed remains unvaried; when it is determined thatthe original seed should be utilized as the input seed, inputting theoriginal seed into the randomizer/derandomizer, in order to generate therandom function according to the original seed to adjust the data; andwhen it is determined that the original seed should not be utilized asthe input seed, inputting a new seed into the randomizer/derandomizer,in order to generate the random function according to the new seed toadjust the data.
 2. The method of claim 1, further comprising: providinga seed generator, wherein the seed generator is arranged to adjust theoriginal seed to generate the new seed.
 3. The method of claim 2,wherein the original seed comprises a plurality of bits, and the newseed comprises a plurality of bits; the seed generator stores one ormore predetermined matrixes; and the method further comprises: utilizingthe original seed and a specific predetermined matrix of the one or morepredetermined matrixes to perform operations, in order to generate thenew seed.
 4. The method of claim 3, further comprising: selecting thespecific predetermined matrix from the one or more predeterminedmatrixes according to at least one index, wherein the at least one indexis utilized for indicating a sector, a word, and/or a byte that the datacorresponds to.
 5. The method of claim 1, wherein the step ofdetermining whether to utilize the original seed as the input seed ofthe randomizer/derandomizer further comprises at least one of the stepsof: when the address falls within a predetermined range, determiningthat the original seed should be utilized as the input seed; and whenthe address does not fall within the predetermined range, determiningthat the original seed should not be utilized as the input seed.
 6. Themethod of claim 5, wherein the predetermined range corresponds to ablock, a page, a sector, or a storage unit that is smaller than thesector.
 7. The method of claim 1, wherein with regard to each page oreach sector of each block, the value of the original seed remainsunvaried.
 8. A memory device, comprising: a Flash memory comprising aplurality of blocks; and a controller arranged to access the Flashmemory and manage the plurality of blocks, and further suppress errorsregarding data accessed by the controller itself, wherein the controllercomprises: a randomizer/derandomizer arranged to generate a randomfunction according to an input seed, with the random function beingutilized for adjusting a plurality of bits of the data bit by bit whenthe controller receives a write/read command, wherein the write/readcommand is utilized for instructing the controller to write the datainto/read the data from the Flash memory, the controller determineswhether to utilize an original seed as the input seed according to anaddress of the data, and with regard to at least each block of theblocks, a value of the original seed remains unvaried; wherein when itis determined that the original seed should be utilized as the inputseed, the controller inputs the original seed into therandomizer/derandomizer, in order to generate the random functionaccording to the original seed to adjust the data; and when it isdetermined that the original seed should not be utilized as the inputseed, the controller inputs a new seed into the randomizer/derandomizer,in order to generate the random function according to the new seed toadjust the data.
 9. The memory device of claim 8, wherein the controllerfurther comprises: a seed generator arranged to adjust the original seedto generate the new seed.
 10. The memory device of claim 9, wherein theoriginal seed comprises a plurality of bits, and the new seed comprisesa plurality of bits; the seed generator stores one or more predeterminedmatrixes; and the seed generator utilizes the original seed and aspecific predetermined matrix of the one or more predetermined matrixesto perform operations, in order to generate the new seed.
 11. The memorydevice of claim 10, wherein the seed generator selects the specificpredetermined matrix from the one or more predetermined matrixesaccording to at least one index; and the at least one index is utilizedfor indicating a sector, a word, and/or a byte that the data correspondsto.
 12. The memory device of claim 8, wherein when determining whetherto utilize the original seed as the input seed of therandomizer/derandomizer, the controller determines based upon at leastone of the steps of: when the address falls within a predeterminedrange, determining that the original seed should be utilized as theinput seed; and when the address does not fall within the predeterminedrange, determining that the original seed should not be utilized as theinput seed.
 13. The memory device of claim 12, wherein the predeterminedrange corresponds to a block, a page, a sector, or a storage unit thatis smaller than the sector.
 14. The memory device of claim 8, whereinwith regard to each page or each sector of each block, the value of theoriginal seed remains unvaried.
 15. A controller of a memory device, thecontroller being utilized for accessing a Flash memory comprising aplurality of blocks, the controller comprising: a read only memory (ROM)arranged to store a program code; a microprocessor arranged to executethe program code to control access to the Flash memory and manage theplurality of blocks, and further suppress errors regarding data accessedby the controller itself; and a randomizer/derandomizer arranged togenerate a random function according to an input seed, with the randomfunction being utilized for adjusting a plurality of bits of the databit by bit when the controller receives a write/read command, whereinthe write/read command is utilized for instructing the controller towrite the data into/read the data from the Flash memory, the controllerdetermines whether to utilize an original seed as the input seedaccording to an address of the data, and with regard to at least eachblock of the blocks, a value of the original seed remains unvaried;wherein when it is determined that the original seed should be utilizedas the input seed, the controller inputs the original seed into therandomizer/derandomizer, in order to generate the random functionaccording to the original seed to adjust the data; and when it isdetermined that the original seed should not be utilized as the inputseed, the controller inputs a new seed into the randomizer/derandomizer,in order to generate the random function according to the new seed toadjust the data.
 16. The controller of claim 15, further comprising: aseed generator arranged to adjust the original seed to generate the newseed.
 17. The controller of claim 16, wherein the original seedcomprises a plurality of bits, and the new seed comprises a plurality ofbits; the seed generator stores one or more predetermined matrixes; andthe seed generator utilizes the original seed and a specificpredetermined matrix of the one or more predetermined matrixes toperform operations, in order to generate the new seed.
 18. Thecontroller of claim 17, wherein the seed generator selects the specificpredetermined matrix from the one or more predetermined matrixesaccording to at least one index; and the at least one index is utilizedfor indicating a sector, a word, and/or a byte that the data correspondsto.
 19. The controller of claim 15, wherein when determining whether toutilize the original seed as the input seed of therandomizer/derandomizer, the controller determines based upon at leastone of the steps of: when the address falls within a predeterminedrange, determining that the original seed should be utilized as theinput seed; and when the address does not fall within the predeterminedrange, determining that the original seed should not be utilized as theinput seed.
 20. The controller of claim 19, wherein the predeterminedrange corresponds to a block, a page, a sector, or a storage unit thatis smaller than the sector.